1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to improvement of a semiconductor memory device having an EDO (Extend Data Out) function.
2. Description of the Background Art
In recent years, various technical developments have been made to improve the data read out speed in a dynamic random access memory (DRAM) which is one semiconductor memory device. General semiconductor integrated circuit devices employ an EDO operation (also referred to as hyper-page operation) to comply with increase in the speed of a read out operation.
The EDO operation includes the step of latching a currently output data until the next data is output, and providing the currently output data. Such an EDO operation can be employed in a DRAM to comply with the high speed read out operation.
FIG. 12 is a block diagram showing a partial structure of a DRAM that carries out an EDO operation. FIG. 12 is provided for the purpose of describing the problems solved by the present invention, and does not show prior art.
Referring to FIG. 12, this DRAM includes a data extending circuit 1, an output buffer circuit 2, a control circuit 3, and an output terminal 6.
Although not shown, this DRAM further includes a plurality of memory cells, each storing 1 bit of data, a row decoder and a column decoder for selecting one of the memory cells, a timing generator responsive to an external control signal for generating an internal control signal, and a preamplifier circuit for amplifying data read out from a selected memory cell.
Data extending circuit 1 responds to an extend control signal .phi.B from control circuit 3 to receive data RDF read out from a memory cell to provide the same as data RD, and latching and outputting that data RD.
Output buffer circuit 2 includes two N channel MOS transistors Q1 and Q2 connected in series between a power supply node and a ground node, inverters I1 and I3 connected to the gate electrodes of transistors Q1 and Q2, respectively, NAND gates G1 and G2 connected to inverters I1 and I3, respectively, and an inverter I2 connected only to one NAND gate G2.
NAND gate G1 receives data RD at its one input terminal. NAND gate G2 receives data RD via inverter I2 at its one input terminal. The other input terminals of NAND gates G1 and G2 receive an output control signal .phi.A from control circuit 3. The common node of transistors Q1 and Q2 is connected to an output terminal 6.
Output buffer circuit 2 responds to output control signal .phi.A from control circuit 3 to be activated, whereby data RD output from data extending circuit 1 is amplified and output via output terminal 6.
Control circuit 3 includes an extend control circuit 4 responsive to an internal row address strobe signal int. RAS, an internal column address strobe signal int. CAS, an internal output enable signal int. OE, and an internal write enable signal int. WE generated by a timing generator (not shown) for generating an extend control signal .phi.B, and an output control circuit 5 responsive to the same control signals int. RAS, int. CAS, int. 0E and int. WE for generating output control signal .phi.A.
A page mode operation of this DRAM will be described hereinafter with reference to the timing chart of FIG. 13.
In a page mode operation, internal column address strobe signal int. CAS falls and rises several times during one fall and rise of internal row address strobe signal int. RAS as shown in (a) and (c) in FIG. 13.
When internal row address strobe signal int. RAS falls, a row address Row input as address signals A0-An shown in FIG. 13(b) is strobed. Then, when internal column address signal int. CAS falls, a column address Col. 1 input as address signals A0-An is strobed.
As a result, one of the plurality of memory cells is selected. As shown in FIG. 13(d), data D1 stored in the selected memory cell is output via output terminal 6 as output data Dout. Similarly, data D2, D3, . . . from the memory cells of different column addresses Col. 2, Col. 3, . . . of same row address Row are output.
In a conventional DRAM, each data D1, D2 and D3 begins to be output in response to a fall of internal column address strobe signal int. CAS, and the output of each data D1, D2, D3 ends in response to a rise of internal column address strobe signal int. CAS, as shown in (b)-(d) of FIG. 13.
As shown in (e)-(i) of FIG. 13, the period Tex of column address strobe signal int. CAS is set shorter than the period Tst shown in FIG. 13(c) to comply with the high speed read out operation.
If data is to be output in response to a fall and rise of an internal column address strobe signal int. CAS as in a conventional case, the output time period of data D1, D2, D3, . . . becomes shorter. It is therefore difficult to obtain valid data.
The DRAM shown in FIG. 12 is formed so that data is continuously latched and output until the next data is output.
More specifically, in the above DRAM, output control signal .phi.A generated by output control circuit 5 rises to a H level (logical high) after a predetermined time period from the fall of both internal row and column address strobe signals int. RAS and int. CAS to a L level (logical low). This output control signal .phi.A is maintained at a H level until internal row and column address strobe signals into RAS and int. CAS both rise to a H level.
Extend control signal .phi.B generated by extend control signal 4 rises and falls in response to the fall and rise, respectively, of internal column address strobe signal int. CAS.
When extend control signal .phi.B rises, data extending circuit 1 provides data RDF read out from a memory cell directly as data RD. In response to the rise of output control signal .phi.A, output buffer circuit 2 is activated. Data RD output from data extending circuit 1 is applied to the gate electrode of transistor Q1 via NAND gate G1 and inverter I1, and is also inverted by inverter I2. The inverted data RD is applied to the gate electrode of transistor Q2 via NAND gate G2 and inverter I3.
As a result, one of transistors Q1 and Q2 is rendered conductive according to data RD, and the other of transistors Q1 and Q2 is rendered nonconductive. Therefore, data Dout of a logic level identical to that of data RD is output via output terminal 6.
When extend control signal .phi.B falls, data extending circuit 1 continues to latch and output data RD. This data RD is output by output buffer circuit 2 via output terminal 6.
When extend control signal .phi.B rises again, data extending circuit 1 receives the next data RDF and provides the same as data RD.
When output control signal .phi.A attains a L level, output buffer circuit 2 is deactivated, whereby a signal of a L level is applied to the gate electrodes of transistors Q1 and Q2, and the common node of transistors Q1 and Q2 attains a floating state. Therefore, output terminal 6 is rendered to a high impedance state Hi-Z.
Because the above-described DRAM carrying out an EDO operation has data extended and output until the next data is output, valid data can easily be obtained.
However, in the above-described DRAM carrying out an EDO operation, output data Dour is extended until the next output data Dout is output. Therefore, output data Dout is fully oscillated instantaneously from a H level to a L level, or from a L level to a H level.
Therefore, there was a problem of ringing R occurring at the beginning of output data Dout, as shown in FIG. 13(i). Because valid output data Dout cannot be obtained until output data Dout becomes stable after this ringing disappears, the read out speed was not substantially increased even though the read out speed was improved by an EDO operation.
Japanese Patent Laying-Open No. 62-12210 and Japanese Patent Laying-Open No. 3-185921 disclose a CMOS type output buffer circuit of a semiconductor integrated circuit device wherein an output signal falls to a L level from a H level or rises to a H level from a L level respectively via a high impedance state.
Also, Japanese Patent Laying-Open No. 3-124120 discloses an output buffer circuit wherein an output signal attaining a H level or a L level is temporarily set to an intermediate level.
Furthermore, Japanese Patent Laying-Open No. 3-23714 discloses an output buffer circuit of an integrated circuit wherein output nodes of two output circuits are connected. The output node is charged in a step-like manner by each output circuit, whereby an output signal thereof temporarily attends an intermediate level when transmitting between an H level and a L level.
All of these are related to an output buffer circuit in a general semiconductor integrated circuit device. In contrast, the present invention is based on a semiconductor memory device such as a DRAM that carries out an EDO operation, and relates to an output buffer circuit thereof.